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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 adf7010 high performance ism band ask/fsk/gfsk transmitter ic features single chip low power uhf transmitter 902 mhz?28 mhz frequency band on-chip vco and fractional-n pll 2.3 v?.6 v supply voltage programmable output power ?6 dbm to +12 dbm, 0.3 db steps data rates up to 76.8 kbps low current consumption 28 ma at 8 dbm output power-down mode (<1 a) 24-lead tssop package applications low cost wireless data transfer wireless metering remote control/security systems keyless entry functional block diagram vco ook/ask ldo regulator muxout lock detect serial interface frequency compensation center frequency fractional n sigma-delta ook/ask pfd/ charge pump r clk pa fsk/gfsk osc1 osc2 clk out cpv dd cp gnd c reg c vco vco gnd v dd rf out rf gnd c reg r set muxout test a gnd ce clk data le txdata txclk d gnd dv dd general description the adf7010 is a low power ook/ask/fsk/gfsk uhf transmitter designed for use in ism band systems. it contains an integrated vco and sigma-delta fractional-n pll. the output power, channel spacing, and output frequency are pro- grammable with four 24-bit registers. the fractional-n pll enables the user to select any channel frequency within the u.s. 902 mhz?28 mhz band, allowing the use of the adf7010 in frequency hopping systems. it is possible to choose from the four different modulation schemes: binary or gaussian frequency shift keying (fsk/ gfsk), amplitude shift keying (ask), or on/off keying (ook). the device also features a crystal compensation register that can provide 1 ppm resolution in the output frequency. indirect temperature compensation of the crystal can be accom- plished inexpensively using this register. control of the four on-chip registers is via a simple 3-wire inter- face. the devices operate with a power supply ranging from 2.3 v to 3.6 v and can be powered down when not in use.
rev. 0 ? adf7010?pecifications 1 (v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25 c.) parameter min typ max unit rf characteristics output frequency ranges u.s. ism band 902 928 mhz phase frequency detector frequency 3.625 20 mhz @ 928 mhz transmission parameters transmit rate fsk 0.3 76.8 kbps ask 0.3 9.6 kbps gfsk 0.3 76.8 kbps frequency shift keying fsk separation 2, 3 1 110 khz, using 3.625 mhz pfd 4.88 620 khz, using 20 mhz pfd gaussian filter t 0.5 amplitude shift keying depth 30 db, max output power 2 dbm on/off keying 40 db output power output power variation max power setting 9 12 dbm, v dd = 3.6 v 11 dbm, v dd = 3.0 v 9.5 dbm, v dd = 2.3 v programmable step size ?6 dbm to +12 dbm 0.3125 db logic inputs v inh , input high voltage 0.7 v dd v v inl , input low voltage 0.2 v dd v i inh /i inl , input current 1 m a c in , input capacitance 10 pf control clock input 50 mhz logic outputs v oh , output high voltage dv dd ?0.4 v, i oh = 500 m a v ol , output low voltage 0.4 v, i ol = 500 m a clk out rise/fall time 16 ns, f clk = 4.8 mhz into 10 pf clk out mark: space ratio 50:50 power supplies voltage supply dv dd 2.3 3.6 v transmit current consumption ?0 dbm (0.01 mw) 12 ma ?0 dbm (0.1 mw) 15 ma 0 dbm (1 mw) 20 ma +8 dbm (6.3 mw) 28 ma +12 dbm (16 mw) 40 ma crystal oscillator block current consumption 190 m a regulator current consumption 380 m a power-down mode low power sleep mode 0.2 1 m a
rev. 0 adf7010 ? parameter min typ max unit phase-locked loop vco gain 80 mhz/v @ 915 mhz phase noise (in-band) 4 ?0 dbc/hz @ 5 khz offset phase noise (out of band) 5 ?00 dbc/hz @ 1 mhz offset spurious 100 khz loop bw integer boundary 6 ?5 dbc, 50 khz loop reference ?0 dbc harmonics 7 ?4 dbc second harmonic v dd = 3.0 v ?7 ?8 dbc third harmonic v dd = 3.0 v ?1 ?8 dbc all other harmonics ?5 dbc reference input crystal reference 3.625 20 mhz external oscillator 3.625 40 mhz input level, high voltage 0.7 v dd v input level, low voltage 0.2 v dd v frequency compensation pull in range of register 1 100 ppm pa characteristics rf output impedance high range amplifier 16 ?j33 w , z ref = 50 w timing information chip enabled to regulator ready 7 50 200 m s crystal oscillator to clk out ok 2 ms, 19.2 mhz xtal temperature range, t a ?0 +85 c notes 1 operating temperature range is as follows: ?0 c to +85 c. 2 frequency deviation = (pfd frequency mod deviation )/2 12 . 3 gfsk frequency deviation = (pfd frequency 2 m )/2 12 where m = mod control. 4 v dd = 3 v, pfd = 19.2 mhz, pa = 8 dbm 5 v dd = 3 v, loop filter bw = 100 khz 6 measured >1 mhz away from integer channel. see successful design with adf7010 transmitter application note. 7 not production tested. based on characterization. specifications subject to change without notice.
rev. 0 ? adf7010 timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth guaranteed by design but not production tested. clock db23 (msb) db22 db2 db1 (control bit c2) data le db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 t 5 figure 1. timing diagram (v dd = 3 v 10%, vgnd = 0 v, t a = 25 c, unless otherwise noted.) absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +4.0 v vcovdd, rfvdd, cpvdd to gnd . . . . . ?.3 v to +7 v digital i/o voltage to gnd . . . . . . ?.3 v to dvdd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +125 c maximum junction temperature . . . . . . . . . . . . . . . . . 125 c tssop ja thermal impedance . . . . . . . . . . . . . . 150.4 c/w csp ja (paddle soldered) . . . . . . . . . . . . . . . . . . . . 122 c/w csp ja (paddle not soldered) . . . . . . . . . . . . . . . . . 216 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performance rf integrated circuit with an esd rating of <1 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = cpgnd = rfgnd = dgnd = agnd = 0 v. ordering guide model temperature range package option adf7010bru ?0? to +85? ru-24 (tssop) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf7010 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. 0 adf7010 ? pin function descriptions pin no. mnemonic function 1r set external resistor to set charge pump current and some internal bias currents. use 4.7 k w as default: i r cp max set = 95 . so, with r set = 4.7 k w , i cpmax = 2.02 ma. 2 cpv dd charge pump supply. this should be biased at the same level as rfv dd and dv dd . the pin should be decoupled with a 0.1 m f capacitor as close to the pin as possible. 3cp gnd charge pump ground 4cp out charge pump output. this output generates current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 5c ec hip enable. a logic low applied to this pin powers down the part. this must be high for the part to function. this is the only way to power down the regulator circuit. 6 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this is a high impedance cmos input. 7 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this is a high impedance cmos input. 8l el oad enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 9t xdata digital data to be transmitted is input on this pin. 10 txclk gfsk only. this clock output is used to synchronize microcontroller data to the txdata pin of the adf7010. the clock is provided at the same frequency as the data rate. 11 muxout this multiplexer output allows either the digital lock detect (most common), the scaled rf, or the scaled reference frequency to be accessed externally. used commonly for system debug. see function register map. 12 d gnd ground pin for the rf digital circuitry 13 clk out the divided down crystal reference with 50:50 mark-space ratio. may be used to drive the clock input of a microcontroller. to reduce spurious components in the output spectrum, the sharp edges can be reduced with a series rc. for 4.8 mhz output clock, a series 50 w into 10 pf will reduce spurs to < ?0 dbc. defaults on power-up to divide by 16. 14 osc2 oscillator pin. if a single-ended reference is used (such as a tcxo), it should be applied to this pin. when using an external signal generator, a 51 w resistor should be tied from this pin to ground. the xoe bit in the r register should set high when using an external reference. pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 tssop adf7010 d gnd muxout txclk txdata le r set cpv dd cp gnd cp out clk ce clk out osc2 osc1 vco gnd test c reg c vco vco in a gnd dv dd rf gnd rf out data
rev. 0 ? adf7010 pin function descriptions (continued) pin no. mnemonic function 15 osc1 oscillator pin. for use with crystal reference only. this is three-stated when an external reference oscillator is used. 16 vco gnd voltage controlled oscillator ground 17 test input to the rf fractional-n divider. this pin allows the user to connect an external vco to the part. disabling the internal vco activates this pin. if the internal vco is used, this pin should be grounded. 18 dv dd positive supply for the digital circuitry. this must be between 2.3 v and 3.6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 19 rf gnd ground for output stage of transmitter 20 rf out the modulated signal is available at this pin. output power levels are from ?6 dbm to +12 dbm. the output should be impedance matched to the desired load using suitable components. see the output rf stage section. 21 a gnd ground pin for the rf analog circuitry 22 vco in the tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (vco). the higher the tuning voltage the higher the output frequency. 23 c vco a 0.22 m f capacitor should be added to reduce noise on vco bias lines. tied to c reg pin. 24 c reg a 2.2 m f capacitor should be added at c reg to reduce regulator noise and improve stability. a reduced capacitor will improve regulator power-on time but may cause higher spurious components.
rev. 0 t ypical performance characteristics?df7010 ? rl = 10.0dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 1khz 915.7mhz span 5.000mhz tpc 1. fsk modulated signal, f deviation = 58 khz, data rate = 19.2 kbps/s, 10 dbm rl = 10.0dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 1mhz rbw = 3khz 915.7mhz span 500khz 2dbm ?6dbm @ 200khz tpc 2. ook modulated signal, data rate = 4.8 kbps/s, 4 dbm start 800mhz stop 7.750ghz + 10dbm second harmonic ?2dbc third harmonic ?4dbc rbw 1.0mhz tpc 3. harmonic levels at 10 dbm output power. see figure 15. 30.00 s 901.000mhz 918.000mhz 935.000mhz 5.00 s ?0.00 s 5.00 s/div v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz tpc 4. pll settling time, 902 mhz to 928 mhz, 23 s ( 400 khz) rbw 100khz span 50.00mhz 915.7mhz + 10dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 100khz +19.2mhz ?1dbc tpc 5. pfd spurious/fractional spurious span 10.00khz 915.7mhz + 10dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 30hz pn @ 4khz 80dbc/hz tpc 6. in-band phase noise
rev. 0 ? adf7010 ch1 500mv c1 freq 1.6mhz m 200ns c1 rise 144.8ns c1 fall 145.6ns c1 +duty 49.385 tpc 7. 1.6 mhz clock out waveform span 5.00mhz 915.7mhz + 10dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 10hz +1.6mhz ?3dbc tpc 8. spurious signal generated by clock out 0.8 0.9 1.0 1.1 1.2 1.3 1.4 frequency ?ghz 0 ? ?0 ?5 ?0 ?5 sensitivity ?dbm tpc 9. n-divider input sensitivity frequency 90 80 885 gain ?mhz/v 70 60 945 925 915 905 895 50 40 100 110 935 v dd = 3v t a = 25 c tpc 10. typical vco gain pa setting ?modulation register 40 level ?dbm ?0 v dd = 2.2v v dd = 3.0v v dd = 3.6v ?5 ?0 ?5 ?0 ? 0 5 10 15 20 60 80 100 120 mid range low range high range tpc 11. pa output programmability, t a = 25 c supply voltage ?v 40 38 2.2 current ?ma 36 34 3.4 3.0 2.8 2.6 2.4 32 30 42 44 3.2 3.6 tpc 12. i dd vs. v dd @ 10 dbm
rev. 0 adf7010 ? register maps rf n register mo dulation register f unction register rf r register f1 r1 11-bit frequency error correction 4-bit r-value db19 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 clk out cl4 xoe reserved c2 (0) c1 (0) control bits db1 db0 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 r2 r3 r4 x1 cl1 cl2 cl3 r1 r2 c2 (0) c1 (1) m1 m12 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n8 db20 db21 db23 db22 vco band ld precision m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 n1 n2 n3 n4 n5 n6 n7 v1 ldp db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) mo dulation deviation m odulation s cheme db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 po wer amplifier db22 db23 i ndex co unter gfsk mod cont rol pre- scaler p1 p5 p6 p7 s1 s2 p1 p2 p3 p4 d1 d2 d3 d4 d5 d6 d7 mc1 mc2 mc3 ic1 ic2 muxout m2 m1 pd1 t est modes c2 (1) c1 (1) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 i1 data in vert db16 pd3 pll e nable clk out e nable pa e nable c harge pump fast lock db17 db22 db21 db20 db19 db23 vco dis able db18 pd2 cp1 cp2 cp3 cp4 vp1 m3 m4 t1 t2 t3 t4 t5 t6 t7 t8 t9 db18 db20 db21 db22 db23 control bits control bits control bits
rev. 0 ?0 adf7010 rf r register 0 ........... 1 1 1 1023 0 ........... 1 1 0 1022 0 ........... . . . . 0 ........... 0 0 1 1 0 ........... 0 0 0 0 e.g., f-counter offset = 1, fractional offset = 1/2 15 f-counter offset f1 f2 f3 f11 ............................................................................................................................... .......................... 1 ........... 1 1 1 1 1 ........... 1 1 0 2 ........... . . . . 1 ........... 0 0 1 1023 1 ........... 0 0 0 1024 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 . . . . . . . . . . . . . . . 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 r4 r3 r2 r1 rf r counter divide ratio 0 xtal oscillator on 1 xtal oscillator off x1 xoe 0 001 2 0 010 4 0 011 6 0 100 8 . ... . . ... . . ... . 1 100 24 1 101 26 1 110 28 1 111 30 div ide ratio cl4 cl3 cl2 cl1 f1 r1 11-bit frequency error correction 4-bit r-value db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 clk out db20 db19 cl4 xoe db21 db23 db22 r eserved c2 (0) c1 (0) c ontrol bits db1 db0 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 r2 r3 r4 x1 cl1 cl2 cl3 r1 r2 clk out
rev. 0 adf7010 ?1 rf n register c2 (0) c1 (1) m1 m12 c ontrol bits 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n8 db20 db21 db23 db22 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 n1 n2 n3 n4 n5 n6 n7 v1 ldp the n-value chosen is a minimum of p 2 + 3p + 3. for prescaler = 8/9 this means a minimum n divide of 91. n counter divide ratio 0 0011111 31 0 0100000 32 0 0100001 33 0 0100010 34 . ....... . . ....... . . ....... . 1 1111101 253 1 1111110 254 1 1111111 255 n8 n7 n6 n5 n4 n3 n2 n1 modulus divide ratio 0 0 0 .......... 1 0 0 4 0 0 0 .......... 1 0 1 5 0 0 0 .......... 1 1 0 6 . . . .......... ... . . . . .......... ... . . . . .......... ... . 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 m12 m11 m10 m3 m2 m1 vco band mhz 0 902?28 1 451?64 lock detect precision 0 3 cycles <15ns 1 5 cycles <15ns e.g., setting f = 0 in fsk mode turns on the sigma-delta while the pll is an integer value e.g., modulus divide ratio = 2048 ? fraction 1/2 ldp v1 vco band ld precision
rev. 0 ?2 adf7010 modulation register d7 d6 . d2 d1 p7 p6 . p2 p1 d7. . . . d3 d2 d1 f deviation if frequency shift keying selected 0 . . . . 0 0 0 pll mode 0 . . . . 0 0 11 f step 0 . . . . 0 1 02 f step 0 . . . . 0 1 13 f step . . . . ............... 1 . . . . 1 1 127 f step d7 d3 d2 d1 divider factor 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 .. .. ...... 11 1 1 127 index counter 0 0 16 0 1 32 1 0 64 1 1 128 gfsk mod c ontrol 000 0 001 1 ... . 111 7 modulation scheme 0 0 fsk 0 1 gfsk 1 0 ask 1 1 ook s2 s1 0 4/5 1 8/9 f step = f pfd /2 12 db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) m odulation deviation db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p ower amplifier db22 db23 i ndex c ounter gfsk mod c ontrol p1 p5 p6 p7 s1 c ontrol bits s2 p1 p2 p3 p4 d1 d2 d3 d4 d5 d6 d7 mc1 mc2 mc3 ic1 ic2 p1 rf prescaler mc3 mc2 mc1 ic2 ic1 power amplifier output level if amplitude shift keying selected, txdata = 0 if gaussian frequency shift keying selected pre- s caler modula tion s chem e 00.x xp a off 01.0 0 16.0dbm 01.0 1 16 1 (10/32) .... .. 01.1 1 16 31 (10/32) 10.0 0 6dbm 10.0 1 6 1 (10/32) .... .. 10.1 1 6 1 (10/32) 11.0 02dbm 11.0 12 1 (10/32) 11.. .. 11.1 1 12dbm 00.x xp a off 01.0 0 16.0dbm 01.0 1 16 1 (10/32) .... .. 01.1 1 16 31 (10/32) 10.0 0 6dbm 10.0 1 6 1 (10/32) .... .. 10.1 1 6 1 (10/32) 11.0 02dbm 11.0 12 1 (10/32) 11.. .. 11.1 1 12dbm
rev. 0 adf7010 ?3 function register m4 m3 m2 m1 muxout 0 0 0 0 logic low 0 0 0 1 logic high 0 0 1 0 three-state 0 0 1 1 regulator ready (default) 0 1 0 0 digital lock detect 0 1 0 1 analog lock detect 0 1 1 0 r divider / 2 output 0 1 1 1 n divider / 2 output 1 0 0 0 rf r divider output 1 0 0 1 rf n divider output 1 0 1 0 data rate 1 0 1 1 logic low 1 1 0 0 logic low 1 1 0 1 logic low 1 1 1 0 normal test modes 1 1 1 1 sigma-delta test modes i1 data invert 0 data 1 data cp2 cp1 i cp (ma) 2.7k 4.7k 10k 0 0 0.50 0.29 0.14 0 1 1.50 0.87 0.41 1 0 2.51 1.44 0.68 1 1 3.51 2.02 0.95 cp4 cp flock down 0b leed off 1b leed on vp1 vco disable 0 vco on 1 vco off mux out t est modes data in vert pll e nable clkout e nable pa e nable c harge pump fast lock vco dis able c ontrol bits t6 t7 t8 t9 r set cp3 cp flock up 0b leed off 1b leed on pd1 pll enable 0 pll off 1 pll on pd2 pa enable 0pa off 1pa on pd3 clk out 0clk out off 1clk out on c2 (1) db19 db18 db17 db16 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db20 db21 db23 db22 t2 t3 t4 t5 t1 m2 m3 m4 m1 vp1 cp4 c2 cp3 c1 pd3 i1 pd2 pd1 c1 (1) db15
rev. 0 ?4 adf7010 default values for registers c2 (0) c1 (1) 0 1 c ontrol bits 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 db20 db21 db23 db22 vco b and ld precis ion n register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mo dulation register db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) m odulation deviation m odulation s cheme db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p ower amplifier db22 db23 i ndex c ounter gfsk mod c ontrol pre- scaler 1 0 1 1 0 c ontrol bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f unction register muxout 1 1 0 t est modes c2 (1) c1 (1) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 0 data in vert db16 1 pll e nable clk out e nable pa e nable c harge pump fa st lock db17 db22 db21 db20 db19 db23 vco dis able c ontrol bits db18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11-bit frequency error correction 4-bit r-value db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 clk out db20 db19 1 xoe db21 db23 db22 r eserved c2 (0) c1 (0) c ontrol bits db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r register
rev. 0 adf7010 ?5 circuit description reference input section the on-board crystal oscillator circuitry (figure 2), allows the use of an inexpensive quartz crystal as the pll reference. the oscillator circuit is enabled by setting xoe low. it is enabled by default on power-up and is disabled by bringing ce low. two parallel resonant capacitors are required for oscillation at the correct frequency; the value of these is dependent on the crystal specification. errors in the crystal can be corrected using the error correction register within the r register. a single- ended reference (tcxo, cxo) may be used. the cmos levels should be applied to osc2, with xoe set high. to r counter, and cl ock out divide buffer sw1 100k 10pf osc2 nc xtal oscillator dis abled 10pf osc1 500k 100k figure 2. oscillator circuit on the adf7010 clk out divider and buffer the clk out circuit takes the reference clock signal from the oscillator section above and supplies a divided down 50:50 mark-space signal to the clk out pin. an even divide from 2 to 30 is available. this divide is set by the 4 msbs in the r register. on power-up, the clk out defaults to divide by 16. clk out dv dd osc1 div ider 1 to 15 div ide by 2 clk out e nable bit figure 3. clk out stage the output buffer to clk out is enabled by setting bit db4 in the function register high. on power-up, this bit is set high. the output buffer can drive up to a 20 pf load with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a small series resistor (50 w ) can be used to slow the clock edges to reduce these spurs at f clk . r counter the 4-bit r counter divides the reference input frequency by an integer from 1 to 15. the divided down signal is presented as the reference clock to the phase frequency detector (pfd). the divide ratio is set in the r register. maximizing the pfd frequency reduces the n-value. this reduces the noise multiplied at a rate of 20 log(n) to the output, as well as reducing occurrences of spurious components. the r register defaults to r = 1 on power-up. prescaler, phase frequency detector (pfd), and charge pump the dual-modulus prescaler ( p/p + 1) divides the rf signal from the vco to a lower frequency that is manageable by the cmos counters. the pfd takes inputs from the r counter and the n counter ( n = int + fraction ) and produces an output proportional to the phase and frequency difference between them. figure 4 is a simplified schematic. cp delay element u3 up charge pump cpgnd v p n divider hi d2 q2 clr2 u2 down hi d1 q1 clr1 u1 r divider r divider n divider cp output figure 4. pfd stage the pfd includes a delay element that sets the width of the antibacklash pulse. the typical value for this in the adf7010 is 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. muxout and lock detect the muxout pin allows the user to access various internal points in the adf7010. the state of muxout is controlled by bits m1 to m4 in the function register. regulator ready this is the default setting on muxout after the transmitter has been powered up. the power-up time of the regulator is typically 50 m s. since the serial interface is powered from the regulator, it is necessary for the regulator to be at its nominal voltage before the adf7010 can be programmed. the status of the regu- lator can be monitored at muxout. once the regulator ready signal on muxout is high, programming of the adf7010 may begin.
rev. 0 ?6 adf7010 digital lock detect digital lock detect is active high. the lock detect circuit is con tained at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until 25 ns phase error is detected at the pfd. since no external components are needed for digital lock detect, it is more widely used than analog lock detect. analog lock detect this n-channel open-drain lock detect should be operated with an external pull-up resistor of 10 k w nominal. when lock has been detected, this output will be high with narrow low going pulses. voltage regulator the adf7010 requires a stable voltage source for the vco and modulation blocks. the on-board regulator provides 2.2 v using a band gap reference. a 2.2 m f capacitor from c reg to ground is used to improve stability of the regulator over a supply from 2.3 v to 3.6 v. the regulator consumes less than 400 m a and can only be powered down using the chip enable (ce) pin. bringing the chip enable pin low disables the regulator and also erases all values held in the registers. the serial interface operates off the regulator supply; therefore, to write to the part, the user must have ce high. regulator status can be monitored using the regulator ready signal from muxout. loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 6. re gulator ready d igital lock detect a nalog lock detect r counter/2 output n counter/2 output r counter output n counter output mux control muxout dgnd dv dd figure 5. muxout stage c harge pump out vco figure 6. typical loop filter configuration third order integrator in fsk, the loop should be designed so that the loop bandwidth (lbw) is approximately 5 times the data rate. widening the lbw excessively reduces the time spent jumping between frequencies but may cause insufficient spurious attenuation. for ask systems, the wider the loop bw the better. the sudden large transition between two power levels will result in vco pulling and can cause a wider output spectrum than is desired. by widening the loop bw to >10 times the data rate, the amount of the vco pulling is reduced, since the loop will settle quickly back to the correct frequency. the wider lbw may restrict the output power and data rate of ask based systems, compared with fsk based systems. narrow loop bandwidths may result in the loop taking long periods of time to attain lock. careful design of the loop filter is critical in obtaining accurate fsk/gfsk modulation. for gfsk, it is recommended that an lbw of 2.0 to 2.5 times the data rate be used to ensure sufficient samples are taken of the input data while filtering system noise.
rev. 0 adf7010 ?7 voltage controlled oscillator (vco) an on-chip vco is included on the transmitter. the vco converts the control voltage generated by the loop filter into an output frequency that is sent to the antenna via the power am plifier (pa). the vco has a typical gain of 80 mhz/v and operates from 900 mhz?40 mhz. the pd1 bit in the func tion register is the active high bit that turns on the vco. a frequen cy divide by 2 is included to allow operation in the lower 450 mhz band. to enable operation in the lower band, the v1 bit in the n register should be set to 1. the vco needs an external 220 nf between the vco and the regulator to reduce internal noise. mux vco select bit to pa and n divider divide by 2 vco control bit loop filter c reg pin 220nf vco figure 7. voltage controlled oscillator rf output stage the rf output stage consists of a dac with a number of cur rent sources to adjust the output power level. to set up the power level: fsk gfsk: the output power is set using the modulation register by entering a 7-bit number into the bits p1?7. the two msbs set the range of the output stage, while the five lsbs set the output power in the selected range. ask: the output power as set up for fsk is the output power for a txdata of 1. the output power for a zero data bit is set up the same way but using the bits d1?7. the output stage is powered down by setting bit pd2 in the function register to zero. p5 p1 p7, p6 high med low figure 8. output stage serial interface the serial interface allows the user to program the four 24-bit registers using a 3-wire interface. (clk, data, and load en able). the serial interface consists of a level shifter, 24-bit shift regis ter, and four latches. signals should be cmos compatible. the serial interface is powered by the regulator, and therefore is inactive when ce is low. table i. c2, c1 truth table c2 c1 data latch 00 r register 01 n register 10 modulation register 11 function register data is clocked into the shift register, msb first, on the rising edge of each clock (clk). data is transferred to one of four latches on the rising edge of le. the destination latch is determined by the value of the two control bits (c2 and c1). these are the two lsbs, db1 and db0, as shown in the timing diagram of figure 1. v dd rf out pa l1 c1 50 l2 figure 9. output stage matching
rev. 0 ?8 adf7010 16 ?j33 5.00 1.00 0.50 0.20 0.00 0.0 0.20 0.50 1.00 2.00 30 40 50 60 70 80 90 100 110 120 130 140 l(series) = 6.8nh 150 2.00 l(shunt) = 12nh 5.00 figure 10. output impedance on smith chart fractional-n n counter and error correction the adf7010 consists of a 15-bit sigma-delta fractional n divider. the n counter divides the output frequency to the output stage back to the pfd frequency. it consists of a prescaler, integer, and fractional part. the prescaler can be 4/5 or 8/9. the spurious performance is better with a 4/5 prescaler, and the n-value can be lower since n min is p 2 + 3 p + 3. the output frequency of the pll is: pfd frequency int fractional error + + () 2 2 3 15 integer n fractional n r reference in n third order - modulator pfd/ charge pump vco figure 11. fractional-n pll fractional-n registers the fractional part is made up of a 15-bit divide, made up of a 12-bit n value in the n register summed with a 10-bit (plus sign bit) in the r-register that is used for error correction, as shown in figure 12. m12 m11 m10 m9 m8 m 7m6m5m4m3m2m1 12-bit n value f10 f9 f8 f 7f6f5f4 10-bit ( sign) error correction f3 f2 f1 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 15-bit fractional n register n2 n1 n0 figure 12. fractional components the resolution of each register is the smallest amount that the output frequency can be changed by changing the lsb of the register. changing the output frequency the fractional part of the n register changes the output fre- quency by: ()( ) fn pfd register value 2 12 the frequency error correction contained in the r register changes the output frequency by: ()( ) f frequency error correction value pfd 2 15 by default, this will be set to 0. the user can calibrate the system and set this by writing a twos complement number to bits f1 C f11 in the r register. this can be used to compensate for initial error, temperature drift, and aging effects in the crystal reference. integer n register the integer part of the n-counter contains the prescaler and a and b counters. it is eight bits wide and offers a divide of p 2 + 3 p + 3 to 255. the combination of the integer (255) and the fractional (31767/ 31768) give a maximum n divider of 256. the minimum pfd usable is: f maximum output frequency pfd (min) () = + required 255 1 for use in the u.s. 902 mhz C 928 mhz band, there is a restriction to using a minimum pfd of 3.625 mhz to allow the user to have a center frequency of 928 mhz. pfd frequency the pfd frequency is the number of times a comparison is made between the reference frequency and the feedback signal from the output. the higher the pfd frequency, the more often a comparison is made at the pfd. this also allows a wider loop bandwidth without compromising stability. this means that the frequency lock time will be reduced when jumping from one frequency to another by increasing the pfd. -
rev. 0 adf7010 ?9 the n divide in the integer part is also reduced. this results in less noise being multiplied from the pfd to the output, resulting in better phase noise for higher pfds. increasing the pfd reduces your resolution at the output. modulation schemes frequency shift keying (fsk) frequency shift keying is implemented by setting the n value for the center frequency and then toggling this with the txdata line. the deviation from the center frequency is set using bits d1?7 in the modulation register. the deviation from the center frequency in hz is: fh z modulation number f deviation pfd () = 2 12 the modulation number is a number from 1 to 127. fsk is selected by setting bits s1 and s2 to zero in the modulation register. r pfd/ charge pump integer n fractional n third order - modulator ? dev +f dev txdata fsk deviation frequency internal vco using spiral inductors gain 70 mhz/v ?90 mhz/v pa stage cheap at crystal vco figure 13. fsk implementation gaussian frequency shift keying (gfsk) gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the txdata. a txclk output line is provided from the adf7010 for syn- chronization of txdata from the microcontroller. the txclk line may be connected to the clock input of an external shift register that clocks data to the transmitter at the exact data rate. shift register adf7010 data from microcontroller txdata txclk antenna figure 14. txclk pin synchronizing data for gfsk setting up the adf7010 for gfsk to set up the frequency deviation, set the pfd and the mod control bits mc1 to mc3: gfsk hz f deviation m pfd () = 2 2 12 where m is mod control. to set up the gfsk data rate: data rate bits s f divider factor index counter pfd () = for further information, refer to the using gfsk on the adf7010 application note. amplitude shift keying (ask) amplitude shift keying is implemented by switching the output stage between two discrete power levels. this is implemented by toggling the dac, which controls the output level between two 7-bit values set up in the modulation register. a zero txdata bit sends bits d1?7 to the dac. a high txdata bit sends bits p1?7 to the dac. a maximum modulation depth of 30 db is possible. ask is selected by setting bit s2 = 1 and bit s1 = 0. on-off keying (ook) on-off keying is implemented by switching the output stage to a certain power level for a high txdata bit and switching the output stage off for a zero. due to feedthrough effects, a maxi- mum modulation depth of 33 db is specified. for ook, the transmitted power for a high input is programmed using bits p1?7 in the modulation register. ook is selected by setting bits s1 and s2 to 1 in the modulation register. choosing channels for best system performance the fractional-n pll allows the selection of any channel within 902 mhz to 928 mhz to a resolution of < 100 hz, as well as facilitating frequency hopping systems. the use of the adf7010 in accordance with fcc part 15.247, allows for improved range by allowing power levels up to 1 w, and greater interference avoidance by changing the rf channel on a regular basis. careful selection of the rf transmit channels must be made to achieve best spurious performance. the architecture of f rac tional-n results in some level of the nearest integer channel moving through the loop to the rf output. these ?eat-note spurs are not attenuated by the loop if the desired rf channel and the nearest integer channel are separated by a frequency of less than the loop bw. the occurrence of beat-note spurs is rare, as the integer frequen- cies are at multiples of the reference, which is typically > 10 mhz. the beat-note spurs can be significantly reduced in amplitude by avoiding very small or very large values in the fractional register. by having a channel 1 mhz away from an integer frequency, a 100 khz loop filter will reduce the level to < ?5 dbc. when using an external vco, the fast lock (bleed) function will reduce the spurs to < ?0 dbc for the same conditions above.
rev. 0 c03143??1/02(0) printed in u.s.a. ?0 adf7010 12nh 6.8nh 100pf 6.2pf 6.2pf 6.8nh cpv dd dv dd rf out r set 4.7k c reg 2.2 f 220nf c vco cp out vco in vco in le clk data ce txdata l ock detect 4.8mh z cl ock mux out clk out 19.2mhz 10pf 10pf test gnd osc2 osc1 50 antenna adf7010 decoupling capacitors have been omitted for clarity. figure 15. application diagram outline dimensions 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards mo-153ad coplanarity 0.10

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